Department of Computer Science and Engineering
Degree Name | Group/Major Subject | Board/Institute | Country | Passing Year |
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No education information is found. |
Title | Organization | Location | From Date | To Date |
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Lecturer | University of Dhaka | 11, Sep 2017 | Currently Working |
Subject | Description | Research Interest (Goal, Target Indicator) |
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Cyber Security | ||
Reconfigurable and Quantum Computing |
Level of Study | Title | Supervisor | Co-Supervisor(s) | Name of Student(s) | Area of Research | Current Completion |
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No project/research supervision is found |
Subject | Project Name | Source of Fund | From Date | To Date | Collaboration |
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No project/research work is found |
SL | Invited Talk |
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No invited talk is found |
SL | Collaboration & Membership Name | Type | Membership Year | Expire Year |
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No Collaboration & Membership is found |
Journal Article | |
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1 |
Mubin Ul Haque, Zarrin Tasnim Sworna, Hafiz Md Hasan Babu, and Ashis Kumar Biswas : A Fast FPGA-Based BCD Adder,
Circuits, Systems, and Signal Processing, Springer, New York, United States , vol.37 , no.10 , pp.4384-4408 , 2018
.
|
2 |
Zarrin Tasnim Sworna, Mubin Ul Haque, Nazma Tara, Hafiz Md Hasan Babu and Ashis Kumar Biswas : Low-power and area effcient binary coded decimal adder design using a look up table-based eld programmable gate array,
IET Circuits,Devices & Systems (United Kingdom) , vol.10 , no.3 , pp.1-10 , 2016
.
|
Conference Proceedings | |
1 |
Zarrin Tasnim Sworna, Mubin Ul Haque and D. M. Anisuzzaman "High-Speed and Area-Effcient LUT-Based BCD Multiplier Design."
WIECON-ECE
IEEE, 2018
.
|
2 |
Zarrin Tasnim Sworna, Mubin Ul Haque and Shahedur Rahman "An FPGA-Based Divider Circuit Using Simulated Annealing Algorithm."
18th International Symposium on Communications and Information Technologies (ISCIT2018)
2018
.
|
Award Type | Title | Year | Country | Description |
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No award information is found |